1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) avoiding circuit, and more particularly, to an ESD avoiding circuit which avoids an ESD current from flowing into a core circuit when the ESD occurs, and provides an operation voltage to the core circuit when working in a regular operation mode.
2. Description of Related Art
In operation, electronic products may suffer ESD, and sometimes are damaged by the ESD affection. ESD usually generates a voltage much larger than voltages provided by ordinary power supplies. As such, when an ESD occurs, the ESD current may burn the component on which it applies. Therefore, ESD protection circuits are usually employed in some circuits for dissipating the ESD current.
FIG. 1 is a circuit diagram of a conventional ESD protection apparatus. Referring to FIG. 1, there is shown an N-type metal oxide semiconductor (NMOS) transistor N0. The NMOS transistor N0 is a metal oxide semiconductor (MOS) transistor having a thick oxide layer. A trigger-on voltage Vt of the NMOS transistor N0 is about 6 to 10 volts, e.g., Vt=8 volts. In a regular operation mode, the core circuit 120 is operated with a predetermined programming voltage. The programming voltage may be a voltage varying according to a clock, a swinging voltage, or a fixed power source voltage. The programming voltage is assumed as a fixed power source voltage, for example 7 volts.
In an ESD mode, as shown in FIG. 1, an ESD high voltage enters from a pad 110. Meanwhile, if the trigger-on voltage Vt of the NMOS transistor N0 is higher than the programming voltage, the ESD current will very likely enter the core circuit 120 before the NMOS transistor N0 is turned on. In other words, the ESD current cannot be guided via the NMOS transistor N0 to a ground voltage trace line VSS. Instead, it enters the core circuit 120 and damages internal components of the core circuit 120.
FIG. 2A is a circuit diagram of a conventional ESD protection apparatus. Referring to FIG. 2A, this conventional ESD protection apparatus utilizes a surface triggering technology to lower the trigger-on voltage of the MOS transistor N0, which is about 1 volt. When working in the ESD mode, an ESD high voltage enters from a pad 210, a high level signal, i.e., a signal of the pad 210, is coupled via a P-type metal oxide semiconductor (PMOS) transistor P1 to a gate of the NMOS transistor N0, so as to conduct the NMOS transistor N0, and thus guiding the ESD current to the ground voltage trace line VSS.
When working in the regular operation mode, the programming voltage enters from the pad 210, an RC circuit composed of a resistor R and a capacitor C provides a high level signal to an input terminal of an inverter 230. The inverter 230 is composed of a PMOS transistor P1 and an NMOS transistor N1. The high level signal is inverted by the inverter 230, and thereafter conducts the NMOS transistor N1, and therefore pulls down a gate voltage of the NMOS transistor N0 to the ground voltage VSS, so that the NMOS transistor N0 is not conducted. In such a way, the NMOS transistor N0 can be prevented from being incorrectly conducted and generating a leak current thereby.
However, a certain time is needed prior to achieving and providing a fixed programming voltage. During the period of boosting the programming voltage, supposing the programming voltage is to be boosted from 0 volt to 3.3 volts, the PMOS transistor P1 inside the inverter 230 may likely be conducted, and further the NMOS transistor N0 is conducted accordingly. Therefore, a part of the leak current will be guided via the NMOS transistor N0 to the ground voltage trace line VSS.
Further, in the regular operation mode, in order to prevent the RC circuit from delaying the signal of the pad 210 and whereby causing a misoperation of the inverter 230, the pad 210 should not be connected to a swinging voltage. FIG. 2B illustrates another coupling configuration of the ESD protection apparatus of FIG. 2A. Referring to FIG. 2B, a pad 240 which is electrically coupled to a stable power source, e.g. 3.3 volts, and the pad 210 is an input pad or an output pad. When working in an ESD mode and the ESD high voltage enters from the pad 210, the pad 240 can be taken as floating connected, and therefore theoretically, an input terminal of the inverter 230 is featured by a low level signal. The low level signal is inverted by the inverter 230, and therefore conducts the NMOS transistor N0, and guides the ESD current to the ground trace line VSS.
According to the configuration shown in FIG. 2B, although when working in the regular operation mode the pad 210 can be electrically connected to a swinging voltage, when a higher programming voltage (comparing with the foregoing power source, assuming the programming voltage is 7 volts hereby) may likely conduct the PMOS transistor P1 inside the inverter 230, and therefore the NMOS transistor N0 is conducted, and thus generating a leakage current thereby.
Further, the NMOS transistor N0 employed in the ESD protection apparatus as shown in FIGS. 1, 2A and 2B are directly coupled to the pads 110, 210. In a typical layout, a silicide block is often used for blocking implanting silicide at a drain of the NMOS transistor N0, and thus increasing the surface resistor of the drain of the NMOS transistor N0. Therefore, in such a way, when an ESD occurs, it can be guaranteed that the ESD current will be guided flowing through a parasite transistor in the NMOS transistor N0 to the ground voltage trace line VSS, rather than flowing through a P-type channel of the NMOS transistor N0, which may damage the gate of the NMOS transistor N0. Likewise, the core circuits 120, 220 are directly coupled to the pads 110, 210, respectively, and source/drains of their internal transistors should also include silicide block for blocking implanting silicide to protect internal gates thereof. However, the implantation of the silicide block directly affects the size of the layout.